As smaller transistors are manufactured, ultra shallow source/drain junctions are becoming more challenging to produce. Generally, sub-100 nm CMOS (complementary metal-oxide semiconductor) devices require a junction depth to be less than 30 nm. Selective epitaxial deposition is often utilized to form epilayers of silicon-containing materials (e.g., Si, SiGe and SiC) into the junctions. Generally, selective epitaxial deposition permits growth of epitaxial layers (“epilayers”) on silicon moats with no growth on dielectric areas. Selective epitaxy can be used to manufacturer features within semiconductor devices, such as elevated source/drains, source/drain extensions, contact plugs or base layer deposition of bipolar devices.
Generally, a selective epitaxy process involves a deposition reaction and an etch reaction. The deposition and etch reactions occur simultaneously with relatively different reaction rates for an epitaxial layer and for a polycrystalline layer. During the deposition process, the epitaxial layer is formed on a monocrystalline surface while a polycrystalline layer is deposited on at least a second layer, such as an existing polycrystalline layer and/or an amorphous layer. However, the deposited polycrystalline layer is generally etched at a faster rate than the epitaxial layer. Therefore, by changing the concentration of an etchant gas, the net selective process results in deposition of epitaxy material and limited, or no, deposition of polycrystalline material. For example, a selective epitaxy process may result in the formation of an epilayer of silicon-containing material on a monocrystalline silicon surface while no deposition is left on the spacer.
Selective epitaxial deposition of silicon-containing materials has become a useful technique during formation of elevated source/drain and source/drain extension features, for example, during the formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. Source/drain extension features are manufactured by etching a silicon surface to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown epilayers, such as a silicon germanium (SiGe) material. Selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during silicide formation increases the series resistance even further. To compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction. Typically, the elevated source/drain layer is undoped silicon.
However, current selective epitaxy processes have some drawbacks. To maintain selectivity during present epitaxial processes, chemical concentrations of the precursors, as well as reaction temperatures must be regulated and adjusted throughout the deposition process. If not enough silicon precursor is administered, then the etching reaction may dominate and the overall process is slowed down. Also, harmful over-etching of substrate features may occur. If not enough etchant precursor is administered, then the deposition reaction may dominate reducing the selectivity to form monocrystalline and polycrystalline materials across the substrate surface. Also, current selective epitaxy processes usually require a high reaction temperature, such as above 800° C., 1000° C. or higher. Such high temperatures are not desirable during a fabrication process due to thermal budget considerations and possible uncontrolled nitridation reactions to the substrate surface. In addition, processing in the conventional manner with simultaneous deposition and etching at temperatures lower than about 800° C. results in unacceptably low growth rates.
Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon-containing compounds. It would be desirable to provide processes for depositing such compounds with optional dopants. Furthermore, the process should be versatile to form silicon-containing compounds with varied elemental concentrations while having a fast deposition rate and maintaining a process temperature, such as about 800° C. or less.